Picture for Yixing Li

Yixing Li

Continuous Speech Tokenizer in Text To Speech

Add code
Oct 22, 2024
Viaarxiv icon

Alignment Between the Decision-Making Logic of LLMs and Human Cognition: A Case Study on Legal LLMs

Add code
Oct 06, 2024
Viaarxiv icon

Direct Preference Knowledge Distillation for Large Language Models

Add code
Jun 28, 2024
Viaarxiv icon

From Isolated Islands to Pangea: Unifying Semantic Space for Human Action Understanding

Add code
Apr 04, 2023
Viaarxiv icon

DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design

Add code
Feb 25, 2023
Viaarxiv icon

Systolic-CNN: An OpenCL-defined Scalable Run-time-flexible FPGA Accelerator Architecture for Accelerating Convolutional Neural Network Inference in Cloud/Edge Computing

Add code
Dec 06, 2020
Viaarxiv icon

Light-Weight RetinaNet for Object Detection

Add code
May 24, 2019
Figure 1 for Light-Weight RetinaNet for Object Detection
Figure 2 for Light-Weight RetinaNet for Object Detection
Figure 3 for Light-Weight RetinaNet for Object Detection
Figure 4 for Light-Weight RetinaNet for Object Detection
Viaarxiv icon

Build a Compact Binary Neural Network through Bit-level Sensitivity and Data Pruning

Add code
Feb 03, 2018
Figure 1 for Build a Compact Binary Neural Network through Bit-level Sensitivity and Data Pruning
Figure 2 for Build a Compact Binary Neural Network through Bit-level Sensitivity and Data Pruning
Figure 3 for Build a Compact Binary Neural Network through Bit-level Sensitivity and Data Pruning
Figure 4 for Build a Compact Binary Neural Network through Bit-level Sensitivity and Data Pruning
Viaarxiv icon

A GPU-Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks

Add code
Jun 08, 2017
Figure 1 for A GPU-Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks
Figure 2 for A GPU-Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks
Figure 3 for A GPU-Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks
Figure 4 for A GPU-Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks
Viaarxiv icon

A Data-Driven Compressive Sensing Framework Tailored For Energy-Efficient Wearable Sensing

Add code
Dec 16, 2016
Figure 1 for A Data-Driven Compressive Sensing Framework Tailored For Energy-Efficient Wearable Sensing
Figure 2 for A Data-Driven Compressive Sensing Framework Tailored For Energy-Efficient Wearable Sensing
Figure 3 for A Data-Driven Compressive Sensing Framework Tailored For Energy-Efficient Wearable Sensing
Viaarxiv icon