Picture for Dylan Rankin

Dylan Rankin

A Neural Network-Based Search for Unmodeled Transients in LIGO-Virgo-KAGRA's Third Observing Run

Add code
Dec 27, 2024
Viaarxiv icon

SymbolFit: Automatic Parametric Modeling with Symbolic Regression

Add code
Nov 15, 2024
Viaarxiv icon

Ultra-low latency recurrent neural network inference on FPGAs for physics applications with hls4ml

Add code
Jul 01, 2022
Figure 1 for Ultra-low latency recurrent neural network inference on FPGAs for physics applications with hls4ml
Figure 2 for Ultra-low latency recurrent neural network inference on FPGAs for physics applications with hls4ml
Figure 3 for Ultra-low latency recurrent neural network inference on FPGAs for physics applications with hls4ml
Figure 4 for Ultra-low latency recurrent neural network inference on FPGAs for physics applications with hls4ml
Viaarxiv icon

Physics Community Needs, Tools, and Resources for Machine Learning

Add code
Mar 30, 2022
Figure 1 for Physics Community Needs, Tools, and Resources for Machine Learning
Figure 2 for Physics Community Needs, Tools, and Resources for Machine Learning
Figure 3 for Physics Community Needs, Tools, and Resources for Machine Learning
Figure 4 for Physics Community Needs, Tools, and Resources for Machine Learning
Viaarxiv icon

Applications and Techniques for Fast Machine Learning in Science

Add code
Oct 25, 2021
Figure 1 for Applications and Techniques for Fast Machine Learning in Science
Figure 2 for Applications and Techniques for Fast Machine Learning in Science
Figure 3 for Applications and Techniques for Fast Machine Learning in Science
Figure 4 for Applications and Techniques for Fast Machine Learning in Science
Viaarxiv icon

hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devices

Add code
Mar 23, 2021
Figure 1 for hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devices
Figure 2 for hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devices
Figure 3 for hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devices
Figure 4 for hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devices
Viaarxiv icon

Fast convolutional neural networks on FPGAs with hls4ml

Add code
Jan 13, 2021
Figure 1 for Fast convolutional neural networks on FPGAs with hls4ml
Figure 2 for Fast convolutional neural networks on FPGAs with hls4ml
Figure 3 for Fast convolutional neural networks on FPGAs with hls4ml
Figure 4 for Fast convolutional neural networks on FPGAs with hls4ml
Viaarxiv icon

Accelerated Charged Particle Tracking with Graph Neural Networks on FPGAs

Add code
Nov 30, 2020
Figure 1 for Accelerated Charged Particle Tracking with Graph Neural Networks on FPGAs
Figure 2 for Accelerated Charged Particle Tracking with Graph Neural Networks on FPGAs
Figure 3 for Accelerated Charged Particle Tracking with Graph Neural Networks on FPGAs
Figure 4 for Accelerated Charged Particle Tracking with Graph Neural Networks on FPGAs
Viaarxiv icon

Distance-Weighted Graph Neural Networks on FPGAs for Real-Time Particle Reconstruction in High Energy Physics

Add code
Aug 08, 2020
Figure 1 for Distance-Weighted Graph Neural Networks on FPGAs for Real-Time Particle Reconstruction in High Energy Physics
Figure 2 for Distance-Weighted Graph Neural Networks on FPGAs for Real-Time Particle Reconstruction in High Energy Physics
Figure 3 for Distance-Weighted Graph Neural Networks on FPGAs for Real-Time Particle Reconstruction in High Energy Physics
Figure 4 for Distance-Weighted Graph Neural Networks on FPGAs for Real-Time Particle Reconstruction in High Energy Physics
Viaarxiv icon

Compressing deep neural networks on FPGAs to binary and ternary precision with HLS4ML

Add code
Mar 11, 2020
Figure 1 for Compressing deep neural networks on FPGAs to binary and ternary precision with HLS4ML
Figure 2 for Compressing deep neural networks on FPGAs to binary and ternary precision with HLS4ML
Figure 3 for Compressing deep neural networks on FPGAs to binary and ternary precision with HLS4ML
Figure 4 for Compressing deep neural networks on FPGAs to binary and ternary precision with HLS4ML
Viaarxiv icon