Picture for Changqing Xu

Changqing Xu

An End-To-End Stuttering Detection Method Based On Conformer And BILSTM

Add code
Nov 14, 2024
Figure 1 for An End-To-End Stuttering Detection Method Based On Conformer And BILSTM
Figure 2 for An End-To-End Stuttering Detection Method Based On Conformer And BILSTM
Figure 3 for An End-To-End Stuttering Detection Method Based On Conformer And BILSTM
Figure 4 for An End-To-End Stuttering Detection Method Based On Conformer And BILSTM
Viaarxiv icon

SLSSNN: High energy efficiency spike-train level spiking neural networks with spatio-temporal conversion

Add code
Jul 14, 2023
Viaarxiv icon

Ultra-low Latency Adaptive Local Binary Spiking Neural Network with Accuracy Loss Estimator

Add code
Jul 31, 2022
Figure 1 for Ultra-low Latency Adaptive Local Binary Spiking Neural Network with Accuracy Loss Estimator
Figure 2 for Ultra-low Latency Adaptive Local Binary Spiking Neural Network with Accuracy Loss Estimator
Figure 3 for Ultra-low Latency Adaptive Local Binary Spiking Neural Network with Accuracy Loss Estimator
Figure 4 for Ultra-low Latency Adaptive Local Binary Spiking Neural Network with Accuracy Loss Estimator
Viaarxiv icon

Ultra-low Latency Spiking Neural Networks with Spatio-Temporal Compression and Synaptic Convolutional Block

Add code
Mar 18, 2022
Figure 1 for Ultra-low Latency Spiking Neural Networks with Spatio-Temporal Compression and Synaptic Convolutional Block
Figure 2 for Ultra-low Latency Spiking Neural Networks with Spatio-Temporal Compression and Synaptic Convolutional Block
Figure 3 for Ultra-low Latency Spiking Neural Networks with Spatio-Temporal Compression and Synaptic Convolutional Block
Figure 4 for Ultra-low Latency Spiking Neural Networks with Spatio-Temporal Compression and Synaptic Convolutional Block
Viaarxiv icon

Self-supervised Point Cloud Registration with Deep Versatile Descriptors

Add code
Jan 25, 2022
Figure 1 for Self-supervised Point Cloud Registration with Deep Versatile Descriptors
Figure 2 for Self-supervised Point Cloud Registration with Deep Versatile Descriptors
Figure 3 for Self-supervised Point Cloud Registration with Deep Versatile Descriptors
Figure 4 for Self-supervised Point Cloud Registration with Deep Versatile Descriptors
Viaarxiv icon

Direct Training via Backpropagation for Ultra-low Latency Spiking Neural Networks with Multi-threshold

Add code
Nov 25, 2021
Figure 1 for Direct Training via Backpropagation for Ultra-low Latency Spiking Neural Networks with Multi-threshold
Figure 2 for Direct Training via Backpropagation for Ultra-low Latency Spiking Neural Networks with Multi-threshold
Figure 3 for Direct Training via Backpropagation for Ultra-low Latency Spiking Neural Networks with Multi-threshold
Figure 4 for Direct Training via Backpropagation for Ultra-low Latency Spiking Neural Networks with Multi-threshold
Viaarxiv icon

A Self Contour-based Rotation and Translation-Invariant Transformation for Point Clouds Recognition

Add code
Sep 15, 2020
Figure 1 for A Self Contour-based Rotation and Translation-Invariant Transformation for Point Clouds Recognition
Figure 2 for A Self Contour-based Rotation and Translation-Invariant Transformation for Point Clouds Recognition
Figure 3 for A Self Contour-based Rotation and Translation-Invariant Transformation for Point Clouds Recognition
Figure 4 for A Self Contour-based Rotation and Translation-Invariant Transformation for Point Clouds Recognition
Viaarxiv icon

Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators using Time Compression Supporting Multiple Spike Codes

Add code
Sep 10, 2019
Figure 1 for Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators using Time Compression Supporting Multiple Spike Codes
Figure 2 for Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators using Time Compression Supporting Multiple Spike Codes
Figure 3 for Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators using Time Compression Supporting Multiple Spike Codes
Figure 4 for Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators using Time Compression Supporting Multiple Spike Codes
Viaarxiv icon