Picture for Takashi Morie

Takashi Morie

Hibikino-Musashi@Home 2024 Team Description Paper

Add code
Oct 08, 2024
Viaarxiv icon

Hibikino-Musashi@Home 2023 Team Description Paper

Add code
Oct 19, 2023
Viaarxiv icon

Learning Reservoir Dynamics with Temporal Self-Modulation

Add code
Jan 23, 2023
Viaarxiv icon

Hibikino-Musashi@Home 2022 Team Description Paper

Add code
Nov 12, 2022
Viaarxiv icon

Hibikino-Musashi@Home 2018 Team Description Paper

Add code
Nov 09, 2022
Viaarxiv icon

Effects of VLSI Circuit Constraints on Temporal-Coding Multilayer Spiking Neural Networks

Add code
Jun 25, 2021
Figure 1 for Effects of VLSI Circuit Constraints on Temporal-Coding Multilayer Spiking Neural Networks
Figure 2 for Effects of VLSI Circuit Constraints on Temporal-Coding Multilayer Spiking Neural Networks
Figure 3 for Effects of VLSI Circuit Constraints on Temporal-Coding Multilayer Spiking Neural Networks
Figure 4 for Effects of VLSI Circuit Constraints on Temporal-Coding Multilayer Spiking Neural Networks
Viaarxiv icon

Hibikino-Musashi@Home 2019 Team Description Paper

Add code
May 29, 2020
Figure 1 for Hibikino-Musashi@Home 2019 Team Description Paper
Figure 2 for Hibikino-Musashi@Home 2019 Team Description Paper
Figure 3 for Hibikino-Musashi@Home 2019 Team Description Paper
Figure 4 for Hibikino-Musashi@Home 2019 Team Description Paper
Viaarxiv icon

Hibikino-Musashi@Home 2020 Team Description Paper

Add code
May 29, 2020
Figure 1 for Hibikino-Musashi@Home 2020 Team Description Paper
Figure 2 for Hibikino-Musashi@Home 2020 Team Description Paper
Figure 3 for Hibikino-Musashi@Home 2020 Team Description Paper
Figure 4 for Hibikino-Musashi@Home 2020 Team Description Paper
Viaarxiv icon

A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design

Add code
Jan 08, 2020
Figure 1 for A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design
Figure 2 for A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design
Figure 3 for A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design
Figure 4 for A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design
Viaarxiv icon

An Efficient Hardware-Oriented Dropout Algorithm

Add code
Nov 14, 2019
Figure 1 for An Efficient Hardware-Oriented Dropout Algorithm
Figure 2 for An Efficient Hardware-Oriented Dropout Algorithm
Figure 3 for An Efficient Hardware-Oriented Dropout Algorithm
Figure 4 for An Efficient Hardware-Oriented Dropout Algorithm
Viaarxiv icon