Picture for Utkarsh Saxena

Utkarsh Saxena

Eigen Attention: Attention in Low-Rank Space for KV Cache Compression

Add code
Aug 10, 2024
Figure 1 for Eigen Attention: Attention in Low-Rank Space for KV Cache Compression
Figure 2 for Eigen Attention: Attention in Low-Rank Space for KV Cache Compression
Figure 3 for Eigen Attention: Attention in Low-Rank Space for KV Cache Compression
Figure 4 for Eigen Attention: Attention in Low-Rank Space for KV Cache Compression
Viaarxiv icon

Hardware/Software co-design with ADC-Less In-memory Computing Hardware for Spiking Neural Networks

Add code
Nov 03, 2022
Viaarxiv icon

On-chip learning in a conventional silicon MOSFET based Analog Hardware Neural Network

Add code
Jul 01, 2019
Figure 1 for On-chip learning in a conventional silicon MOSFET based Analog Hardware Neural Network
Figure 2 for On-chip learning in a conventional silicon MOSFET based Analog Hardware Neural Network
Figure 3 for On-chip learning in a conventional silicon MOSFET based Analog Hardware Neural Network
Figure 4 for On-chip learning in a conventional silicon MOSFET based Analog Hardware Neural Network
Viaarxiv icon

On-chip learning for domain wall synapse based Fully Connected Neural Network

Add code
Nov 25, 2018
Figure 1 for On-chip learning for domain wall synapse based Fully Connected Neural Network
Figure 2 for On-chip learning for domain wall synapse based Fully Connected Neural Network
Figure 3 for On-chip learning for domain wall synapse based Fully Connected Neural Network
Figure 4 for On-chip learning for domain wall synapse based Fully Connected Neural Network
Viaarxiv icon