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Steve Wilton

Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting

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Nov 23, 2024
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ZOBNN: Zero-Overhead Dependable Design of Binary Neural Networks with Deliberately Quantized Parameters

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Jul 06, 2024
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QUTE: Quantifying Uncertainty in TinyML models with Early-exit-assisted ensembles

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Apr 19, 2024
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DNN Memory Footprint Reduction via Post-Training Intra-Layer Multi-Precision Quantization

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Apr 03, 2024
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T-RECX: Tiny-Resource Efficient Convolutional Neural Networks with Early-Exit

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Jul 14, 2022
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MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications

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Jul 08, 2021
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