Picture for Igor Loi

Igor Loi

Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode

Add code
Oct 18, 2021
Figure 1 for Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
Figure 2 for Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
Figure 3 for Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
Figure 4 for Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
Viaarxiv icon

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

Add code
Apr 23, 2017
Figure 1 for An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
Figure 2 for An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
Figure 3 for An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
Figure 4 for An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
Viaarxiv icon