FOGNA: An effective Sum-Difference Co-Array Design Based on Fourth-Order Cumulants

Array structures based on the fourth-order difference co-array (FODCA) provide more degrees of freedom (DOF). However, since the growth of DOF is limited by a single case of fourth-order cumulant in FODCA, this paper aims to design a sparse linear array (SLA) with higher DOF via exploring different cases of fourth-order cumulants. This paper presents a mathematical framework based on fourth-order cumulant to devise a fourth-order extend co-array (FOECA), which is equivalent to FODCA. A novel SLA, namely fourth-order generalized nested array (FOGNA), is proposed based on FOECA to provide closed-form expressions for the sensor locations and enhance DOF to resolve more signal sources in direction of arrival (DOA) estimation. FOGNA is consisted of three subarrays, where the first is a concatenated nested array and the other two subarrays are SLA with big inter-spacing between sensors. When the total physical sensors of FOGNA are given, the number of sensors in each subarray is determined by the designed method, which can obtain the maximum DOF under the proposed array structure and derive closed-form expressions for the sensor locations of FOGNA. The proposed array structure not only achieves higher DOF than those of existing FODCAs but also reduces mutual coupling effects. Numerical simulations are conducted to verify the superiority of FOGNA on DOA estimation performance and enhanced DOF over other existing FODCAs.

BadHMP: Backdoor Attack against Human Motion Prediction

Precise future human motion prediction over subsecond horizons from past observations is crucial for various safety-critical applications. To date, only one study has examined the vulnerability of human motion prediction to evasion attacks. In this paper, we propose BadHMP, the first backdoor attack that targets specifically human motion prediction. Our approach involves generating poisoned training samples by embedding a localized backdoor trigger in one arm of the skeleton, causing selected joints to remain relatively still or follow predefined motion in historical time steps. Subsequently, the future sequences are globally modified to the target sequences, and the entire training dataset is traversed to select the most suitable samples for poisoning. Our carefully designed backdoor triggers and targets guarantee the smoothness and naturalness of the poisoned samples, making them stealthy enough to evade detection by the model trainer while keeping the poisoned model unobtrusive in terms of prediction fidelity to untainted sequences. The target sequences can be successfully activated by the designed input sequences even with a low poisoned sample injection ratio. Experimental results on two datasets (Human3.6M and CMU-Mocap) and two network architectures (LTD and HRI) demonstrate the high-fidelity, effectiveness, and stealthiness of BadHMP. Robustness of our attack against fine-tuning defense is also verified.

A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing

Wireless baseband processing (WBP) is a key element of wireless communications, with a series of signal processing modules to improve data throughput and counter channel fading. Conventional hardware solutions, such as digital signal processors (DSPs) and more recently, graphic processing units (GPUs), provide various degrees of parallelism, yet they both fail to take into account the cyclical and consecutive character of WBP. Furthermore, the large amount of data in WBPs cannot be processed quickly in symmetric multiprocessors (SMPs) due to the unpredictability of memory latency. To address this issue, we propose a hierarchical dataflow-driven architecture to accelerate WBP. A pack-and-ship approach is presented under a non-uniform memory access (NUMA) architecture to allow the subordinate tiles to operate in a bundled access and execute manner. We also propose a multi-level dataflow model and the related scheduling scheme to manage and allocate the heterogeneous hardware resources. Experiment results demonstrate that our prototype achieves $2\times$ and $2.3\times$ speedup in terms of normalized throughput and single-tile clock cycles compared with GPU and DSP counterparts in several critical WBP benchmarks. Additionally, a link-level throughput of $288$ Mbps can be achieved with a $45$-core configuration.