Picture for Sharad Sinha

Sharad Sinha

AaP-ReID: Improved Attention-Aware Person Re-identification

Add code
Sep 27, 2023
Viaarxiv icon

Joint-YODNet: A Light-weight Object Detector for UAVs to Achieve Above 100fps

Add code
Sep 27, 2023
Viaarxiv icon

YOLORe-IDNet: An Efficient Multi-Camera System for Person-Tracking

Add code
Sep 23, 2023
Viaarxiv icon

Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System

Add code
Dec 11, 2020
Figure 1 for Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System
Figure 2 for Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System
Figure 3 for Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System
Figure 4 for Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System
Viaarxiv icon

Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA

Add code
Sep 03, 2020
Figure 1 for Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA
Figure 2 for Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA
Figure 3 for Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA
Figure 4 for Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA
Viaarxiv icon

An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power

Add code
Sep 03, 2020
Figure 1 for An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power
Figure 2 for An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power
Figure 3 for An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power
Figure 4 for An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power
Viaarxiv icon

Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA

Add code
Sep 03, 2020
Figure 1 for Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA
Figure 2 for Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA
Figure 3 for Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA
Figure 4 for Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA
Viaarxiv icon

FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications

Add code
Jul 01, 2020
Figure 1 for FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications
Figure 2 for FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications
Figure 3 for FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications
Figure 4 for FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications
Viaarxiv icon

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis

Add code
May 06, 2019
Figure 1 for Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
Figure 2 for Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
Figure 3 for Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
Figure 4 for Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
Viaarxiv icon