Real-time Event Recognition of Long-distance Distributed Vibration Sensing with Knowledge Distillation and Hardware Acceleration

Distributed optical fiber vibration sensing (DVS) technology based on phase-sensitive optical time-domain reflectometry is widely used for safety monitoring and intrusion event surveillance in wide-ranging fields. Existing methods rely on deep learning models for event recognition but struggle with real-time processing of large data volumes in long-distance applications. To address these challenges, we use a four-layer convolutional neural network (CNN). The application of knowledge distillation with ResNet as the teacher model improves the generalization ability of the four-layer CNN, increasing the accuracy from 83.41% to 95.39% on data from untrained environments. The model is implemented on a field programmable gate array (FPGA) using a novel design that replaces multiplication with binary shift operations and quantizes model weights accordingly, allowing for high parallelism and low latency. An inference time of 0.083 ms is achieved for a spatial-temporal sample with a 12.5 m fiber length and 0.256 s time frame. This implies the system can process signals over a fiber length of approximately 38.55 km in real time, which is more than twice the capability of a GPU of Nvidia GTX 4090. The proposed method greatly improves the efficiency of vibration pattern recognition, thus promoting the application of DVS as smart sensing system in various areas. The data and code is available at https://github.com/HUST-IOF/Efficient-DVS

Real-time FPGA Implementation of CNN-based Distributed Fiber Optic Vibration Event Recognition Method

Utilizing optical fibers to detect and pinpoint vibrations, Distributed Optical Fiber Vibration Sensing (DVS) technology provides real-time monitoring and surveillance of wide-reaching areas. This field has been leveraging Convolutional Neural Networks (CNN). Recently, a study has accomplished end-to-end vibration event recognition, enabling utilization of CNN-based DVS algorithms as real-time embedded system for edge computing in practical application situations. Considering the power consumption of central processing unit (CPU) and graphics processing unit (GPU), and the inflexibility of application-specific integrated circuit (ASIC), field-Programmable gate array (FPGA) is the optimal computing platform for the system. This paper proposes to compress pre-trained network and adopt a novel hardware structure, to design a fully on-chip, pipelined inference accelerator for CNN-based DVS algorithm, without fine tuning or re-training. This design allows for real-time processing with low power consumption and system requirement.An examination has been executed on an existing DVS algorithm based on a 40-layer CNN model comprising 2.7 million parameters. It is completely implemented on-chip, pipelined, with no reduction in accuracy.