Picture for Joanna Kolodziej

Joanna Kolodziej

Performance Modelling of Deep Learning on Intel Many Integrated Core Architectures

Add code
Jun 04, 2019
Figure 1 for Performance Modelling of Deep Learning on Intel Many Integrated Core Architectures
Figure 2 for Performance Modelling of Deep Learning on Intel Many Integrated Core Architectures
Figure 3 for Performance Modelling of Deep Learning on Intel Many Integrated Core Architectures
Figure 4 for Performance Modelling of Deep Learning on Intel Many Integrated Core Architectures
Viaarxiv icon

Customizing Pareto Simulated Annealing for Multi-objective Optimization of Control Cabinet Layout

Add code
Jun 04, 2019
Figure 1 for Customizing Pareto Simulated Annealing for Multi-objective Optimization of Control Cabinet Layout
Figure 2 for Customizing Pareto Simulated Annealing for Multi-objective Optimization of Control Cabinet Layout
Figure 3 for Customizing Pareto Simulated Annealing for Multi-objective Optimization of Control Cabinet Layout
Figure 4 for Customizing Pareto Simulated Annealing for Multi-objective Optimization of Control Cabinet Layout
Viaarxiv icon